Binary Phase Shift Keying BPSK Modulation Demodulation Computer Science Essay

Binary Phase Shift Keying BPSK Modulation De chanting Computer Science screenThis experiment is based on the Binary Phase Shift Keying (BPSK) modulation/demodulation technique. The aim of the experiment is to gain familiarity with the components of a simple data contagion system, gain experience using an data-based communication system and perusing its performance under the influence of white disagreement and alike, to compargon experimental results with theoretical deductions.Bandpass modulation, of which BPSK is a type, is a knead whereby, a sinusoid usually called a carrier wave, is modulated or have its characteristics lurchd by a digital cadence baseband manoeuvre in other to enable radiocommunication based transmission. In BPSK modulation, the phase of the carrier waveform is shifted to either 0 or clxxx by the modulating data level.To effectively model the transmission credit line, the AWGN generator is used which adds the effect of noise to the request at the telephone receiver in other to properly characterise what obtains in trustworthy systems. SNR measurements atomic number 18 taken after the noise is added before the receiver and results of each make up of the experiment are presented.2.0 RESULTS AND DISCUSSIONThe results obtained from the experiment and brief discussions are nowadays presented.2.1 The oftenness of the waveform was metric to be 1.493kHz2.2 The amplitude of the waveform was careful to be 3.608V2.3CDocuments and SettingsAGEBNIGADesktopLAB RESULTSPart 2.bmpFig. 1 Square Waveform from NE555 epochkeeper circuit.The timer circuit modernises a sequence of ones and naughts which together with the resistors and capacitor, produces a square waveform. It git be observed that the square top and bottom are non perfectly straight but with riffs, this is due to the resonance effect presented by the capacitor. Also, the rising pattern of the top is due to the electric potential rise time in the capacitor.2.4 The ab solute absolute oftenness of the message sequence is measured to be 374Hz2.5CDocuments and SettingsAGEBNIGALocal SettingsTemporary lucre FilesContent.WordPart 4 5.bmpFig. 2 Message sequence at the siding of the frequency divider.The SN74LS74 integrated circuit implements a blink of an eye order frequency divider, 2n (n=2). Hence the frequency of the timer circuit is divided by four. Hence, this is also seeming(a) in the frequency of the message sequence in 2.4 above.2.6 The cut-off frequency of the 2nd order Butterworth low pass separate out is given byThe cut-off frequency is the frequency at which the magnitude of the transfer function drops to 0.7071 of its maximal evaluate which represents the point at which the power in the circuit is 3dB slight than the maximum value.2.7 The frequency of the sinusoid at the output of the filter was measured to be 1.328kHz.2.8 CDocuments and SettingsAGEBNIGALocal SettingsTemporary meshing FilesContent.Wordpart 8.jpgFig. 3 Output of t he first and second Butterworth LPF. A BA Output of first filter B Output of second filterThe Butterworth lowpass filter is used to generate the curved carrier required for the baseband signal. The Butterworth filter has a gentle roll-off, has no ripple in the pass or stop band wherefore, it has a categoric response. To maximise the smoothness of the sinusoid, we use two of such filters in series.2.9 The RC heightspass filter is used to remove the DC components of the sinusoid (since it ordain only fall by the wayside frequencies from the cut off frequency upwards) and convert it into a non-return to zero one. The cut-off frequency is given by2.10 The frequency of the modulated signal was measured to be 1.408kHz.2.11 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 11.bmpFig. 4 Output of the RC filter and the inverting amplifier circuits. A BA RC filter output B Inverting amplifier outputThe outputs of the RC filter and the inverting am plifier disaccord by a phase shift of 180, to fulfil the emergency for BPSK where we need antipodal modulated signals. Since the gain of the inverting amplifier is unity, there is no change to the amplitude of the inverted carrier.2.12 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 10 12.bmpFig. 5 BPSK signal at the output of the adder circuit. AThe analogue switch produces a 0 shifted sinusoid when the message signal is high (a 1) and a 180 shifted sinusoid when the message signal is low (a 0). The two outputs bombards are feature in the adder circuit which has a gain of unity so that no modification is made to the signal amplitude. The result of this is a stream of 1s and 0s represented by the sinusoidal waveform in fig. 5 above. dot A depicts the sudden phase change as the bits changes to connote a transition from a high to a low and vice-versa.If we begin with a 1, then the fig. 4 would represent 10101010.2.13 The bandwidth of the nois e signal is 500kHz.2.14 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 14.jpgFig. 6 BPSK signal with white noise.The AWGN channel helps to simulate what can typically obtain in real communication environments and it was observed that in real systems, the signal is not really as elegant as presented in fig. 5 but the addition of noise means the receiver will require some form of intelligence and signal processing in other to correctly detect the transmitted message.2.15CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 15.jpgFig. 7 BPSK rackety signal at output of RC lowpass filter.The cut-off frequency of this filter is given by hence it will cut off signals above 15.92kHz. It was observed that after the application of this filter, the noise level was significantly reduced as evident comparing fig. 6 and 7, since the noise contained a large amount of frequency components higher than 15.92kHz due to its bandwi dth of 500kHz.2.16 The signal at the output of the integrator takes the specify of a sawtooth waveform. This is because integrating a square waveform produces a sawtooth waveform.2.17CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 16 17.bmpFig. 8 Output of the integrator circuit. A BThe multiplier and integrator circuit represents a matched filter implementation at the receiver. Point A represents the zero point i.e the beginning of a spic-and-span symbol or bit in this case, when the integrator is re-set. As such, when a 1 changes to a 0, we have a re-set to zero point and the burster of the triangular shape changes to the opposite.Point B is the integ balancen phase proper. It is not smooth due to the effect of noise in the system. Also, the rise is a direct result of the capacitor charging.2.18 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 18.jpgFig. 9 pound application to integrator. A BA Integrat or output B Reset capriceAs displayed on fig. 8 above, the reset pulse is applied to the integrator at the symbol transition instant which is seen to be the beginning of every half cycle to reset the integrator to zero.2.19 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 19a.pngFig. 10 The Reference SignalCDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.Word19b.jpgFig. 11 The Sampling winkCDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 19c.jpgFig. 12 The Reset PulseThe reference signal is obtained from the SN74LS74 frequency divider of the transmitter thus it is the primitively transmitted message sequence. The sampling and reset instances are done at the analogous time that is at the half cycle.2.20 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 20.jpgFig. 13 Output of the Comparator.This is where the original baseband signal is regener ated. From fig. 8, when the output of the integrator is positive, an output fivesomeage of 5 volts is produced at the comparator and when the integrator output is negative, a 0 volt output is obtained. This resulted in fig. 13 above showing the alternating 5 and 0 volts or 1s and 0s which depicts our detected signal. The frequency of the detected signal is 1.419kHz.2.21 The length of the sticked version of the data symbol produced at the receiver is 1.804ms2.22 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 21 and 22 Greeen channel 2 yellow channel 1.bmpFig. 14 The Delayed pulse and Original data signal. A BA- Delayed Pulse B Original PulseComparing the original data signal against the retard version, it is observed that though they are of the same period, B has longer duration positive half cycle bit A compensates with a longer negative half cycle. Also, the time delay between them is about a half cycle.2.23 CDocuments and SettingsAGEBNI GALocal SettingsTemporary Internet FilesContent.WordPart 23 yellow delay green comparator.bmpFig. 15 arousal Signals to the XOR circuit. A BA Delayed original signal B Detected signalThe detected signal B is compared against the delay version of the original signal A, because B generally, B would have experienced some delay and hence to effectively ascertain if an error occurred, its best to compare it against a delayed original as represented by A. The exclusivity of the circuit lies in the circumstance that when A B are the same, a 0 will be produced while when they are different denoting an error, a 1 will be produced.2.24 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 24 green 2 yellow 1.jpgFig. 16 Input Signals to the first NAND gate. A BA Sampling Pulse B XOR OutputA NAND gate will only produce a zero when both inputs are high. Hence a zero is obtained when the sampling instant coincides with a high output from the XOR circuit.2.25 CDocuments and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 25 yellow chn1 5v dc green chn2 1st input.pngFig. 17 Input Signals to the second NAND gate. A B CA Input 5Vdc B Output of first NAND gate C Zero pointSince a NAND gate will produce a high when both inputs are not the same and when they are both 0, a 5V dc (always high or 1) is applied to one of the inputs and the output of the first NAND gate to the other. Hence, at the points where B comes down to zero (C), the output of the NAND gate will disk a high which implies an error has occurred.2.26To estimate the BERWhere Vs (rms value of signal amplitude) =514mV,Vn (rms value of noise amplitude) = 0-10dBW (AWGN channel bandwidth) = 500kHzT (modulated Signal period) = 656.25sSNR get signal to noise ratioBER bit error rate or error probability.Table 1 below presents the values.Table 1 stocky of ResultsFig. 18 BER Performance Plot3.0 CONCLUSIONThe BER performance plot of fig. 18 shows that the behav iour of the experimental system is within the bounds of predicted theoretical results. For instance, as quoted in the lecture notes, at SNR= 10.4dB, the BER is about 1.510-6. From fig.18 above, a similar point, of SNR=10.3806dB gives a BER of 1.48810-6. Hence confirming the accuracy of the results obtained from the experiment. The plot confirms that as the signal-to-noise ratio increases, the error probability reduces in line with conventional knowledge.In addition, the process of using a baseband signal to modulate the phase of a sinusoid was observed, converting it into a bandpass signal for transmission ease.Also, the use of Additive White Gaussian Noise to simulate the channel provides an insight into what might be pass judgment in a live system environment, under varying degrees of noise exposure.Finally, because the received data sequence will most likely be displaced from its true positions as demonstrated experimentally, the use of a time delayed version of the original tra nsmitted sequence to compare and check for errors was justified.